Conventional field effect transistors have uniformly doped channel regions. Source/drain regions are implanted and diffused on either side of a polysilicon gate structure. A channel implant step adjusts the threshold voltage of the transistor and produces channel doping which is symmetrically distributed between the source and the drain. Generally, similar processing steps are followed for producing uniformly doped p-channel and n-channel transistors in complementary metal-oxide-semiconductor (CMOS) processes.
Symmetric channel doping has required a tradeoff between maximum drive current, I.sub.Dsat, and leakage current, I.sub.Doff. Channel (loping is necessary to limit leakage current in the transistor. Leakage current is the current which flows from source to drain when zero gate to source bias is applied. Minimum leakage current is necessary to limit overall power dissipation in a large scale integrated circuit using many thousands of transistors. However, the channel doping required to limit or control leakage current has the deleterious effect of reducing drive current, which is the current available from the transistor to drive a load. Maximum drive current is necessary to maximize the speed of operation of circuits incorporating the transistor. The tradeoff between leakage current and drive current becomes more severe in deep-submicron transistors, i.e., those with gate lengths below 0.15 .mu.m.
Recently, asymmetrical channel profiles have been proposed for deep-submicron field effect transistors. Such devices have features which make them advantageous for integrated circuit performance. In particular, asymmetric devices allow for increased drain current (I.sub.Dsat), which in turn affords higher operational speeds. The asymmetrical channel is achieved by an ion implantation step. This implantation step may replace the implant for the symmetric channel doping or it may be used in addition to that implant.
However, this additional ion implantation step tends to increase manufacturing costs. Additional mask steps are required to define the ion implantation windows for each required transistor orientation. Each additional mask step increases cost and misalignment risk. Misalignment of the masks used for asymmetric channel implant can impair performance of the finished transistor. This is inconsistent with a goal of minimizing masking steps to minimize manufacturing costs.
Accordingly, there is a need for a method for manufacturing field effect transistors having asymmetrical channel profiles which minimizes additional masking steps and manufacturing costs.